1. Field of the Invention
The present invention relates to a plurality of novel and unique methods and arrangements for measuring the cooling rate and thermal gradient between the top and bottom of a printed circuit board. Moreover, the invention is intended to facilitate control over the temperature gradient which is encountered between the top and bottom of the PCB so as to prevent warpage thereof during the formation of solder joints in a reflow solder oven.
In the implementation of soldering procedures, for example, in reflow soldering ovens, which are employed in the soldering of high-mass printed circuit boards, particularly when these PCBs are equipped with high-mass ceramic CCGA or CBGA modules, there have been ascertained unique types of solder failures which are encountered in the formation of solder joints for producing electrical interconnections, and which are frequently referred to as solidification stress fractures. There are three types of failure mechanisms that can result;
(a) Solidification fractures, time-zero fails (any solder fillet). PA1 (b) Stretched or disturbed joints, reliability exposure (any solder fillet). PA1 (c) Brittle cracked columns, time-zero fails (Solder column modules only). PA1 (a) PCB thickness; inasmuch as thicker boards can support a larger temperature difference between the top or upper surface and the bottom surface; PA1 (b) The mass, density and placement of components on the printed circuit board; whereby the greater mass and density retains more heat on the top side or upper surface in comparison with the bottom side or surface. PA1 (c) Cool-down rate; wherein higher cooling rates exaggerate the instantaneous temperature differential between the top or upper and the bottom surfaces of the printed circuit board. PA1 (d) The employment of direct impingement fans in order to cool the upper and/or lower PCB surfaces; whereby one surface is cooled significantly faster than the other (instantaneously or during the entire cool down period) due to differences in PA1 (a) The solder fillets; subject to solidification fractures or disturbed joints in critical temperature range 190.degree. C.&gt;T (temperature of the solder joint)&gt;170.degree. C. PA1 (b) The solder columns (CCGA components); subject to brittle cracking in the critical temperature range 190.degree. C.&gt;T (temperature of the column)&gt;180.degree. C.
These modes or soldering failure has been investigated in the technology, and shown to be highly dependent upon the cooling rate and thermal gradient extending through the thickness of the printed circuit board during corner solder joint solidification. An aspect is which has been ascertained in cases of stress fracture failure has been the occurrence of a clean fracture which is produced between the intermetallic (Cu--Sn) material on the card pad and the solder material which is in the fillet. The result of the foregoing can be either an almost immediate time-zero (instantaneous) electrical open solder connection, or a latent reliability fail which necessitates cycling in order to become electrically open. The time-zero opens are characterized by gaps of up to 1 mil, which may occur on only a single solder joint which is surrounded by a large number of so-called "stretched" solder joints. The reliability failures have been separated through less than 100% of the soldered area and do not evidence any measurable gap until failure early during temperature cycling.
In essence, when a thermocoupled profile card is conducted or conveyed, such as on a belt or conveyor, through a furnace; for instance, an infrared (IR)/convection oven which is known to produce stress fracture interconnections, there has been indicated the presence of a sharp transient thermal spike, when thermocouple data is collected and plotted/analyzed as prescribed herein. This particular temperature spike is believed to be responsible for inducing printed circuit board (PCB) warpage at a critical period in time when module solder joints; especially at a corner and periphery, are at the verge of solidification, thereby resulting in this type of failure mode on nearly joints that have solidified.
For example, in cases where a wire is soldered to a CCGA pad, and shortly after solidification, it has been ascertained that the solder joint strength is extremely low; for example, approaching only a few grams. Moreover, from modeling studies, there has been indicated a variation in card warpage, which may be on the order of 1 mil. Thus, when these experimental observations are combined, confirmation is had that this can readily result in an occurrence of stress fracture types of solder joint failure.
Another aspect of these particular solder failures which may not be readily apparent after assembly of the PCB components, resides in that the application of PCB deformation during solder joint solidification; in effect, warping of the PCB, can readily weaken any resulting electrical interconnection of the components.
As indicated, the process causing solder joint failure and related influencing factors are essentially as follows:
1. The temperature differential (.DELTA.T.sub.z =T.sub.top -T.sub.bot) which is created extending through the thickness of the PCB (the Z-axis) during the cooling segment of the conveyor belt or rail driven oven reflow cycle. The temperature on the upper surface of the printed circuit board can be significantly higher or lower than that on the bottom surface, depending on which surface cools more rapidly. One surface will cool faster than the other due to oven factors (forced air rate/volume/temperature, belt effects, etc.) and product attributes (component density and thermal mass). Thus, the magnitude of this Z-axis thermal differential (.DELTA.T) is a function of PA0 2. Differential thermal expansion between upper and lower board surfaces due to Z-axis temperature differential causes the printed circuit board to warp practically instantaneously, thereby imparting a load or stress on some of the solder joints. PA0 3. The instantaneous warping of the printed circuit board with respect to the modules or components which are positioned thereon creates a displacement and a resultant load which can readily produce a disturbed or fractured solder joint, depending upon the timing and the temperature of: PA0 4. The result of the foregoing is a time-zero electrical opening of the joints (or columns), and/or early life cycle reliability failures. PA0 1. average delta-T (.DELTA.T) of all pairs of thermocouples is less than 6.degree. C. PA0 2. No single delta-T (.DELTA.T) is greater than 10.degree. C.
(1) Design and use of top versus bottom fans; staggered location of top/bottom fans, differences in airflow, and balanced use (some ovens have fans only on one side or the other). PA2 (2) Design and use of oven belt or work board holder on which PCB is placed; can impede airflow more from one side than the other. PA2 (3) Layout of components on PCB top and/or bottom surface, which can also impede airflow locally across PCB.
In case of a positive .DELTA.T.sub.z or change in the positive direction, the top side or upper surface of the printed circuit board expands at a greater rate than the bottom surface, causing the PCB to warp or bend concavely downwardly. In effect, below a module site, the PCB moves away from the component at corner and edge solder joints.
Although considerations have been given in the technology towards improving the reliability of solder joints on printed circuit boards, and particularly in monitoring and possibly regulating encountered temperature differentials as the printed circuits boards are conveyed through infrared ovens or solder reflow ovens on conveyor belts, transport rails or the like, these generally do not readily provide for simple remedial methods measures and arrangements which enable correction of the temperature spike problems which are encountered during soldering sequences and which cause PCT warping and resultant solder joint failures.
2. Discussion of the Prior Art
Bast et al., U.S. Pat. No. 5,647,667 discloses an arrangement for the proof testing of ceramic parts. Utilized is an acceptance stress test in which a stress is generated by a temperature distribution on a part through thermal radiation. The stress is then characterized in order to validate the test. Although the temperature distribution is characterized similarly to the process employed in the present invention as between various component regions, there is no teaching of a method and algorithm for the profiling of a printed circuit board transported through a reflow solder oven in order to obtain results which will be indicative of any temperature spikes tending to warp a PCB and adversely affect the integrity of solder joints and electrical connects.
Ume, U.S. Pat. No. 5,601,364 discloses a method and apparatus for measuring thermal warpage including a test setup and apparatus for producing shadow moire measurements on printed circuit boards over a given time interval and temperature profile. The temperature profile obtained thereby is a highly simplified simulation of an actual reflow oven, such as is obtained from typical oven profile cards. Although, the patent evaluates printed circuit board warpage for a desired temperature profile over a period of time, there is no disclosure of positioning thermocouples in a unique manner on opposite surfaces of a printed circuit board for detecting specific failure mechanisms, nor is the thermal gradient (.DELTA.T.sub.z) through the PCB thickness ascertained.
Ito, U.S. Pat. No. 5,630,667 merely discloses a modeling method for predicting heat cracking through three-dimensional polymer model constituted of photo-set resins having a particular thermal conductivity in order to identify hot spots which may be susceptible to heat cracking; for example, such as exhaust manifolds.
Marcantonio, U.S. Pat. No. 5,562,243 discloses a method and apparatus for reflow temperature settings, in which an artificial network provides for the reflow oven settings for acceptable soldering of printed circuit boards based on inputted thermal/physical features and feedback "learning". There is no disclosure of the utilization of thermocouples on opposite PCB surfaces for detecting specific failure mechanisms when measuring temperature at the upper and lower surfaces of the printed circuit board.
Similarly, O'Rourke, et al., U.S. Pat. No. 4,180,199 also merely describes a mass soldering system for measuring temperature as a function of time through a wave soldering process, and does not direct itself to a method and arrangement pursuant to the present invention.